1. Field of the Invention
The present invention relates to a flip-flop circuit, and more particularly to a flip-flop circuit capable of preventing data signal propagation delays by reducing the number of stages of logic circuits located on a data signal input path.
2. Description of the Related Art
A CMOS flip-flop circuit, provided with three functions for a test operation, clear operation and output feedback operation in addition to data input operation, is widely used in a semiconductor integrated circuit. Referring to FIG. 1A, a CMOS flip-flop circuit will be described. FIG. 1A is a circuit diagram illustrating a CMOS flip-flop circuit.
As shown, the CMOS flip-flop circuit 1 mainly comprises an input signal selection section 2 and a latch circuit 3. The input signal selecting section 2 includes selection circuits 2-1–2-3 and inverters 2-4 and 2-5. The selection circuit 2-1 is a multiplexer, for example. This circuit selects either the inverted output signal QN of the CMOS flip-flop or an input data signal DI inverted by the inverter 2-4. The selection circuit 2-2 is a NAND gate, for example. This circuit selects either the signal selected by the selection circuit 2-1 or a reset signal RN inverted by the inverter 2-5. The selection circuit 2-3 is a multiplexer, for example. This circuit selects either the signal selected by the selection circuit 2-2 or a test signal TI. The latch circuit 3 is of a master-slave type, for example. This circuit latches the signal selected by the selection circuit 2-3.
The usual operation of the CMOS flip-flop circuit 1 constructed as above is the data input operation. When executing the data input operation, an enable signal Enb for controlling the selection circuit 2-1 is asserted. As a result, the selection circuit 2-1 selects the input data signal DI inverted by the inverter 2-4. The input data signal DI is latched by the latch circuit 3 via the selection circuits 2-2 and 2-3.
When executing the clear operation, the reset signal RN is asserted. As a result, the output of the selection circuit 2-2 is forcibly fixed. The output signal of the selection circuit 2-2 is latched by the latch circuit 3 via the selection circuit 2-3. Thus, the data latched by the latch circuit 3 is reset.
When executing the test operation, a test enable signal TE input to the selection circuit 2-3 is asserted. As a result, the selection circuit 2-3 selects the test signal TI, and the latch circuit 3 latches the test signal TI.
Further, the CMOS flip-flop circuit 1 executes an output feedback operation in addition to the aforementioned three operations. The output feedback operation is executed to secure an output state even if there is no input signal. When there is no input signal, the selection circuit 2-1 selects the inverted output signal QN of the latch circuit 3. The latch circuit 3 again latches the inverted output signal QN via the selection circuits 2-2 and 2-3.
The order of priority of the four above-mentioned operations is test operation, clear operation and enable/data-input operations. In other words, even if the reset signal RN or input data signal DI is input, the test operation is executed unconditionally as long as the test enable signal TE is asserted. If, on the other hand, the test enable signal is not asserted, the reset operation is executed in preference to the output feedback operation or data input operation.
More specifically, as shown in FIG. 1B, when fixing an order of priority to signals input to the flip-flop circuit, a selection circuit MUX1 is used to select one of two signals IN(1) and IN(2), which have the lowest priority. After that, a selection circuit MUX2 is used to select one of the elected signal and a signal IN(3) having the second lowest priority. Similarly, selection circuits MUX3–MUX(n−2) execute signal selection. The selection circuit MUX(n−1) of the last stage selects either a signal IN(n) of the highest priority or the output signal of the selection circuit MUX(n−2). By virtue of this structure, it can be determined, in accordance with a control signal Cnt(n−1) for the selection circuit MUX(n−1) of the last stage, whether or not the signal IN(n) of the highest priority should be selected, irrespective of the states of the selection circuits MUX1–MUX(n−2).
FIG. 1C is a timing chart illustrating the waveforms of a clock CP and the input data signal DI. The input data signal DI is normally captured by the flip-flop circuit in synchronism with the clock CP. As shown, when the input data signal DI is captured in synchronism with the leading edge of each pulse of the clock CP, it is necessary to input the input data signal DI to the flip-flop circuit before the rise of each pulse of the clock CP. The time required from the input of the input data signal DI to the rise of each pulse of the clock CP is called a “setup time”. The reason why the setup time is provided is that determined time is required until the input data signal DI is actually captured by the flip-flop circuit after it is input. Therefore, the longer the input path of the input data signal, the longer the setup time should be.
In the case of the flip-flop circuits shown in FIGS. 1A and 1B, the input path of a signal selected by a selection circuit of a later stage is very long. For example, in the flip-flop circuit shown in FIG. 1A, the input data signal DI must pass through the selection circuits 2-2 and 2-3 before it reaches the latch circuit. Thus, the input path of the input data signal DI is long and hence the setup time should be set long. Where the setup time is long, it may impede an increase in the operation speed of the flip-flop circuit. Furthermore, it requires a large operational margin and hence may make the circuit design complicated.
FIG. 1D is a block diagram illustrating a semiconductor integrated circuit. As shown, the semiconductor integrated circuit comprises flip-flop circuits 1-1–1-4, and logic circuits 4-1–4-2 to be controlled by the outputs of the flip-flop circuits. When executing a test operation, the test signal TI is input to each flip-flop 1-1–1-4, and the test operation is executed in synchronism with the clock CP.
Usually, the propagation speed of the test signal TI is very high since the signal propagates through a test signal path wired by a dedicated wiring method. On the other hand, the clock CP has a skew, which may involve a problem during the operation of each flip-flop. Specifically, there is a case where the test signal TI reaches a flip-flop circuit earlier than the clock CP. For example, in the case of FIG. 1D, the test signal TI reaches each flip-flop 1-1–1-4 circuit earlier than the clock CP. Therefore, it is possible that the reliability of the test operation will be significantly degraded.
This clock skew problem can be solved by inserting a delay cell only in the test signal path. In this case, however, the whole circuit size will be inevitably large, and further, it is necessary to review the design of the entire flip-flop structure so as to insert a delay cell. Therefore, the insertion of a delay cell is not a preferable solution.